Non-Patent Document 1 describes an example of delay model of Field Programmable Gate Array (FPGA). In the delay model described in this document, delay of individual elements of logic element is given by a reference table which includes constant value independent of positions on the array. Delay on wiring routes herein is calculated based on a delay calculation model called Elmore delay model, and is characterized by a constant value independent of positions on the array.
Patent Document 1 (Japanese Laid-Open Patent Publication No. 2004-102739) and Patent Document 2 (Japanese Laid-Open Patent Publication No. 2008-123458) describe a delay analysis based on extraction of a parasitic device.